module pipeline_reg2 #(
  parameter WIDTH = 1
)(
  input clk,
  input rst,
  input we,
  input dsel,
  input [WIDTH-1:0] d0,
  input [WIDTH-1:0] d1,
  output reg [WIDTH-1:0] q
);

always @(posedge clk) begin
  if (rst) begin
    q <= 0;
  end else if (we) begin
    q <= dsel ? d1 : d0 ;
  end
end

endmodule
